8 Conclusions

When a VLSI system is being developed, the designer must make sure an implementation meets all design goals, including performance goals. Here we present a set of algorithms which use the performance description language PDL to generate constraint satisfaction problems upon which the performance goals can be directly asserted. Algorithms then check these CSPs for satissability. If a CSP is satissable, the original VLSI system can meet its performance goals. These algorithms use interval analysis as an evaluation mechanism and maintain close ties to the CSP notions of consistency. Thus, it is easy to determine if PDL-derived CSPs evaluated by these algorithms are satissable. CSPs are evaluated using interval squeezing to establish consistency. These algorithms are being implemented as a back-end extension to the PDL environment. Eventually PDL models will be partially evaluated and generate CSP systems instead of attribute dependency graphs. This will allow a designer to take an implementation of a VLSI system, use PDL to generate the corresponding CSP, and assert design goals on this CSP. These algorithms can then be used to return a `Yes/No' answer to the designer, answering the question \Are these design goals possible with this implementation?" This eventually can be implemented in a high-level synthesis tool to automatically determine which synthesized results are unacceptable, and which may be preferrable over the others. Both of these are useful applications of these algorithms.